
%Preamble
While modeling the device-to-architecture abstraction for steep slope processors, the contribution of noise and variations can play a significant role at various levels.
%The sensitivity of communications systems is limited by noise~\cite{lee-jssc2000}. 
%For embedded systems which include analog or RF blocks, e.g. amplifiers, analog-to-digital converters (ADCs) and voltage-controlled oscillators (VCOs), noise is a key factor that limits the overall system performance in terms of dynamic range, signal-to-noise ratio (SNR), phase noise, etc. 
%When the embedded system is powered by weak or intermittent energy sources like RF signals, thermo-electricity, or solar cells, the harvested power and the supply voltage are low. As a result, the maximum analog signal amplitude limited by the supply voltage results in challenges for these noise-sensitive designs.
Electrical noise has a significant impact on systems which have limited signal amplitude due to a low-voltage power supply. On the other hand, device-level variations, when coupled with variations in the manufacturing process, can manifest themselves at the circuit and architectural levels for a whole range of applications. Our studies show that CMOS and TFET-based processors are affected to different degrees by these variations over different supply voltage ranges.
In this section, we examine the impact of noise and device-level variations on CMOS and TFET devices in the different application domains discussed in the paper. 

With the scaling of technology nodes, electrical noise imposes a growing reliability issue due to the increased sensitivity of circuit performance and reduced signal range at low $V_{DD}$~\cite{Ghibaudo2002}. 
For embedded wireless transceiver systems, the analog and RF front-end blocks are crucial in that they usually consume a considerable fraction of the overall power budget. The presence of noise in these blocks thus limits the overall system power efficiency and performance specifications including the signal bandwidth, signal-to-noise ratio (SNR), dynamic-range (DR), etc. When the embedded system is powered by weak or intermittent energy sources like ambient RF signals, thermo-electricity, or solar cells, the maximum signal amplitude, as well as the harvested power and the supply voltage, are lowered. Some signals are intrinsically weak, e.g. bio-signals. In such scenarios, the performance in the presence of noise suffers, especially when the supply voltage is low. 
%Therefore, the analog and RF front-end blocks face the challenge of realizing a noise-affected low-supply, low-power design. We shall subsequently examine the impact of noise on TFET performance and the noise-related design challenges in typical analog and RF front-end blocks, including amplifiers, LC oscillators, and analog-to-digital converters (ADCs).

The analog and RF frontend blocks thus face the challenge of realizing a noise-affected, low-supply, low-power design, and the tradeoff between power and noise is a key consideration. Consequently, it is of great importance to evaluate the electrical noise characteristics for steep-slope devices while pursuing power reduction in embedded systems. We shall subsequently examine the impact of noise on the performance of TFET-based systems, with the noise-related design challenges in TFET amplifiers as an example.

%In energy harvesting and bio-signal acquisition applications, the weak nature of bio-signals gives rise to growing demands of ultra-low power, low-noise circuits for front-end signal processing and data conditioning. Tradeoffs between power and noise are one of the key limitations in CMOS based low-power analog/mix-signal system design. Thus, it is of great importance to evaluate the electrical noise characteristics for steep-slope devices while pursuing the significant power reduction in RF powered system. 

Low frequency noise characterization for different types of TFETs has been reported in~\cite{BijeshDRC2012,FanTED2013}, showing strongly process dependent noise characteristics. The analytical models on flicker, shot and thermal noise were developed in~\cite{RahulTED2013} for III-V HTFET. 
The simulation results reveal that at a nominal operation voltage of 0.3~V, HTFET exhibits competitive input referred noise as compared to Si-FinFET in KHz and MHz frequency range.  
Due to the presence of increased shot noise due to the tunnel junction, however, the input referred noise of HTFET increases moderately at operating voltage exceeding 0.3~V and frequency range of 10~GHz or higher. 
The resultant noise figure of III-V HTFET fulfills the bandwidth requirement of ultra-low voltage sensor node applications.

\subsection{Effect of noise in amplifier design}
\begin{figure}[ht!]
\centering
\epsfig{file=figs/amplifier.eps, angle=0, width=0.5\linewidth, clip=}
\caption{\label{fig:amplifier} A typical fully differential amplifier}
\end{figure}

Figure~\ref{fig:amplifier} shows a typical fully differential amplifier. It is well known that the input referred noise of the CMOS amplifier is given by the equation:
\small
\begin{equation}
d\overline{\nu_{n,in}^2} = 2\bigg(\frac{4kT\gamma}{g_{m1}} + \frac{K_{fn}/2K_n}{(WL)_1C_{ox}f}+\frac{g_{m3}^2}{g_{m1}^2}\Big(\frac{4kT\gamma}{g_{m3}} + \frac{K_{fp}/2K_p}{(WL)_1C_{ox}f}\Big)\bigg)df
\end{equation}
\normalsize

where $g_m$ is the transconductance, WL is the transistor area, f is frequency, and $K_{fn}$, $K_n$, and $C_{ox}$ are device-related constant parameters. Further, the dynamic range of the amplifier can be derived as:

\small
\begin{equation}
DR = \frac{\frac{1}{2}v_{sig}^2}{\overline{\nu_{n,in}^2}} = \frac{V_{out}^2}{2A\overline{\nu_{n,in}^2}}
\end{equation}
\normalsize

where A is the amplifier gain. In order to reduce the input noise and increase the dynamic range, larger input $g_m$ is required. However, for a power-sensitive design, a large current might not be efficient to boost the transconductance. Therefore, a trade-off occurs between low power and low noise. In this case, the steep-slope TFET offers a higher current efficiency in terms of $g_m/I_{ds}$ while providing the same transconductance~\cite{RahulTED2013}.

%\item{\textbf{LC oscillators:}}
%Low-noise RF circuits are critical in low-bit-rate data transmission for embedded systems. For LC oscillators, the phase noise dominates at frequencies near the carrier. In~\cite{lee-jssc2000}, it has been revealed that, for an LC oscillator in Figur~\ref{fig:oscillators}b), the phase noise L (representing the frequency offset from the oscillation frequency 0) has a -10 dB/decade dependence on the power of the signal (carrier) $P_{sig}$.
%
%\small
%\begin{equation}
%L{\Delta\omega} = 10\log\Bigg[\frac{2FkT}{P_{sig}}\bigg(1+\big(\frac{\omega_0}{2Q\Delta\omega}\big)^2\bigg)\bigg(1+\frac{\Delta\omega_{1/f^3}}{\left|\Delta\omega\right|}\bigg)\Bigg]
%\end{equation}
%\normalsize
%
%\begin{figure}[ht!]
%\centering
%\epsfig{file=figs/oscillators.eps, angle=0, width=1\linewidth, clip=}
%\caption{\label{fig:oscillators} a) A typical fully differential amplifier  b) An RLC oscillator}
%\end{figure}
%\item{\textbf{ADCs:}}
%One main error source in ADCs is the $kT/C$ sampling noise due to the thermal noise of sampling switch resistance. The limited supply voltage for low-power considerations results in lower signal amplitude, and also smaller sampling capacitance C. Consequently, the $kT/C$ noise is increased, and the ratio of the signal to the sampling noise is thus reduced.
%\end{itemize}
%
